This invention relates to a custom semiconductor integrated circuit device.
Today's complex and highly integrated Application Specific Integrated Circuit (ASIC) or System On Chip (SoC) may contain multiplicities of reusable intellectual properties (IPs) such as central processing units (CPUs), memories, high-speed transceivers and other full-custom or semi-custom functional blocks, among others. These IP blocks may be independently designed and implemented with a full-custom methodology or a semi-custom methodology such as standard cell technology or gate array technology with potentially more than two metal layers and via layers. For example, one common functional block found in an ASIC or a SoC design may be a RAM block. The RAM blocks may be a full-custom design or metal programmable design and may potentially contain three or more metal and via layers. It is also very common that today's ASIC or SoC may contain more than 5 or 6 metal layers and up to 10 metal layers, depending on the complexity of the designs.
One well known and commonly used approach in making highly integrated ASICs or SoCs is standard cell technology. This technology may provide a high degree of flexibility since all layers (active and interconnect layers) are completely customizable. As a result, the standard cell approach often achieves the most optimized die size, the highest performance, and the easiest integration of IPs. However, in standard cell technology, each layer requires a different mask to project a pattern on the silicon wafer to create an integrated circuit and in today's advanced IC fabrication process nodes (e.g. 45 nm), the cost of masks may easily exceed over a million dollars per mask set. Hence, standard cell technology is becoming unsuitable for the realization of many ASIC or SoC in terms of time and cost.
To overcome the shortcomings of standard cell technology, particularly high mask cost and long manufacturing time for ASICs or SoCs, metal programmable technologies such as gate array and structured ASIC technology have been suggested. The advantages of metal programmable technologies may include reduced manufacturing time and mask cost since there may be a portion of the fixed mask layers that is design independent and only metal or via layers need to be customized to create an ASIC or SoC. In metal programmable technology, the multiplicities of base cell may be in non-programmable layers (e.g. fixed region) and the customization of the base cell may be only performed by metal or via layers. Additionally, the ASIC or SoC devices using metal programmable technology may contain multiplicities of IP blocks which may already contain many metal layers that may be non-customizable since these metal layers are intrinsic parts of the IP blocks and may not be modified when they are integrated into an ASIC or a SoC.
FIG. 1A illustrates an exemplary stack of layers which may be used to manufacture an integrated circuit 100 using traditional gate array technology. Fixed region 200 may contain substrate layer 201, diffusion layer 202, and gate electrode layer 203 to form P and N type MOS transistors. The layers in fixed region 200 may not be customizable or may not be changed. Hence, the available transistors or base cells may be predetermined and may be pre-fabricated on wafers and may be customized or programmed at later time by customizing layers in programmable region 210. Traditional gate array technology may result in a reduced number of layers compared to standard cell technology since the layers in fixed region 200 would be common in implementing integrated circuit 100.
FIG. 1B illustrates an exemplary layout diagram of two inputs NAND circuit using traditional gate array technology. The most commonly used gate array base cell contains two P-type MOS transistors 21 and two N-type MOS transistors 22. These transistors may be formed with substrate layer 201, diffusion layer 202, and gate electrode layer 203, which are part of fixed region 200 in FIG. 1A. In this illustration, the design connects various P-type MOS nodes to N-type MOS nodes using contact layer 205 and metal layer 211 which are part of programmable region 210 to create the NAND function circuit.
There have been many attempts in metal programmable technology to provide potential advantages for smaller die size and for better performance but still may maintain potential advantage of metal only programmable technology. U.S. Pat. Nos. 5,341,041; 5,289,021; 4,816,887; 5,038,192; and 4,668,972 disclose many different gate array base cell architecture and different size transistors in base cell to enhance gate density (e.g. die size). U.S. Pat. No. 6,617,761 discloses two different types of base cells to increase gate density and elevated metal levels for customization to enhance global routing and time to market problems of standard cell and gate array technology. U.S. Pat. Nos. 7,463,062; 6,985,012; 6,930,511; 6,194,912 discloses metal programmable integrated circuit which may be customized by single via layers with lookup table (LUT) base cells which are common in Field Programmable Gate Array (FPGA). These disclosures may result in a single mask programmable IC, which reduces the mask cost. However, such devices may rely on larger base cells such as LUTs as compared to transitional gate array. Additionally, such devices may not offer the density, power and performance comparable to standard cell technology. U.S. Pat. Nos. 7,870,513 and 4,910,417 disclose various base cells that may contain multiplexors, simple combination logic cells, or inverters to minimize the number of programmable mask layers, but these base cells still do not offer the same density, power, and performance of standard cell technology.